Digital electronic logic devices, such as microprocessors, field-programmable gate arrays (“FPGAs”), complex logic devices (“CPLDs”), and application-specific integrated circuits (“ASICs”) use a digital clock signal to synchronize operations of different portions of the logic device. Generally, the digital clock signal enables logic and memory cells to read and write data at the appropriate times.
“Setup time” and “hold time” describe the timing requirements on the data input of a sequential logic element, such as a flip-flop or register, with respect to a clock input. The set-up and hold times define a window of time during which data must be stable to guarantee predictable performance over a full range of operating conditions and manufacturing tolerances. The setup time is the minimum amount of time that an input data signal must be held steady before a clock event, such as a rising or falling edge of a clock signal, in order for the state of the data signal to be reliably captured. Hold time is the minimum amount of time the input data signal should be held steady after the clock event in order for the state of the data signal to be reliably captured. A setup time violation, which is sometimes referred to as a long path problem, can be remedied by reducing the path length or reducing the clock speed. A hold time violation, which is sometimes referred to as a short path problem, can be remedied by increasing the path length or adding delay circuitry to the signal path.
Timing analysis performed during place-and-route CAD processes identifies and attempts to remedy timing violations in a circuit design. However, current approaches require significant computing resources and may produce unsatisfactory results.